The present invention relates to an Exclusive-OR gate circuit and more particularly to a 3-input CMOS type Exclusive-OR gate circuit which is particularly adapted for combining with other like circuits in a parity checking circuit configuration.
Parity checking circuits verify the correct operation of a data processing system by completing the count for a group of bits such that a correct group of bits and the parity bit will always be, for example, an even count. A single bit error will make the count odd, thereby indicating the existence of the error. Generally speaking, a data processing system is designed to operate on groups of 8 bits, each commonly called a byte. Each group of 8 bits has 1 parity bit appended to it, such that each group of 9 error free bits always includes an even or an odd number of 1's depending on the type of parity convention designed into the processor.
Traditional implementations of parity circuits use 8, 2-input Exclusive-OR gates for processing a byte (8 bits) and an associated parity bit (1 bit). The present inventive circuit is configured to receive three input signals. The traditional implementations experience a significant delay in signal processing because of the large number of gates used. It is therefore, highly desirable to use the least number of gates to accomplish the desired Exclusive-OR function with the least amount of signal delay.
A patent of particular interest for its teaching of an Exclusive-OR circuit that may be used in a parity checking circuit and for an extensive listing of prior art publications is U.S. Pat. No. 4,430,737 entitled, "Exclusive-OR Circuit and Parity Checking Circuit Incorporating the Same" by H. Beranger et al.
Another patent of interest is U.S. Pat. No. 4,319,148, entitled, "High Speed 3-Way Exclusive-OR Logic Circuit" by S. D. Malaviya wherein is disclosed a circuit which performs an OR function with a delay essentially equal to that experienced in a single logic stage.
Another patent of interest is U.S. Pat. No. 4,417,161 entitled, "Complemetary Channel Type MOS Transistor Exclusive-OR/NOR Logic Gate Circuit" by M. U. Kadoma wherein is disclosed a two input Exclusive-OR gate which is implemented in CMOS with a reduced number of transistors from that of conventional circuits.
Other patents of interest are U.S. Pat. Nos. 4,651,296 entitled, "High Speed CMOS FET Full-Adder Circuit" by H. Koike which is implemented in CMOS logic and 4,626,711, entitled, "Exclusive-OR Gate Circuit", by G. M. Li which discloses an Exclusive-OR gate that is suitable for use as a parity bit generator.